1. Field of the Invention
The present invention relates to a phase comparator for use in a phase-locked loop and the like and, more particularly, to a phase comparator having two different phase comparison characteristics.
2. Description of the Related Art
In an integrated circuit for write/read control in a magnetic disk or an integrated circuit for communication control, not only a pulse signal waveform having a duty ratio of 50%, but also a signal waveform (a pulse signal waveform having a duty ratio of less than 50%), is sometimes used in a certain time period, although the signal waveform changes in accordance with the type of modulating system. In order to perform phase comparison for such a signal waveform by using a phase comparator, phase comparison must be performed only when an input pulse is present. A phase-locked loop having two phase comparison characteristics for a pulse signal having a duty ratio of 50% and a pulse signal having a duty ratio of less than 50% is described in, e.g., U.S. Pat. No. 4,593,254. A "VCO centering circuit" described in U.S. Pat. No. 4,593,254 has a first phase comparator for receiving a reference pulse signal having a duty ratio of 50% as a comparison input signal from a quartz oscillator and a second phase comparator for receiving reception data having a duty ratio of less than 50% as a comparison input signal. Outputs from the first and second phase comparators are subjected to a selection operation by a multiplexer. That is, this multiplexer selects one of the outputs from the first and second phase comparators. An output from the multiplexer is converted into a predetermined signal waveform by a charge pump circuit. An output from the charge pump circuit is smoothed into a DC signal by a low-pass filter. An output from the low-pass filter is supplied to a voltage-controlled oscillator (to be abbreviated to as a VCO hereinafter). A signal having a frequency corresponding to the output level from the low-pass filter is generated by the VCO and supplied as a comparison reference signal to the first and second phase comparators.
When a phase of the comparison reference signal (output signal from the VCO) leads ahead of that of the comparison input signal, the first and second phase comparators output control signals for delaying the phase of the output signal from the VCO. When the phase of the output signal from the VCO lags behind that of the comparison input signal, the first and second phase comparators output control signals for advancing the phase of the output signal from the VCO. The charge pump circuit outputs a signal of the positive or negative level in a time period corresponding to a duration of the control signal for advancing or delaying the phase of the signal selected by the multiplexer and keeps an output node in a floating state in the other period.
In the phase-locked loop having the above arrangement, however, since two phase comparators each having a comparatively large number of elements are used, the number of constituting elements of the circuit is increased. In addition, if the first and second phase comparators are constituted by a CMOS circuit, although consumption power is low when the loop is used in a low-frequency region, it is largely increased in a high-frequency region. If the first and second phase comparators are constituted by a TTL (transistor-transistor logic) circuit or an ECL (emitter-coupled logic) circuit, although consumption power is not much increased in a high-frequency region unlike in a CMOS circuit, a considerable amount (larger than the amount used in a CMOS circuit) of power is consumed throughout low to high-frequency regions.